关于FPGA中[寄存器初值]&[Reset]的一些思考

关于FPGA中[寄存器初值]&[Reset]的一些思考

本文依然是基于FPGA实测中遇到的一个问题:如果我的板子上没有按钮或者开关,那么我应该如何进行寄存器的初始化或Reset操作?最容易想到的方法就是对通过晶振产生的时钟进行计数,从而使一个1bit寄存器输出一个脉冲信号。那么,计数所需要的寄存器是否是我们已知的值?请继续阅读。

xilinx FPGA是否可以指定register初值

原文https://forums.xilinx.com/t5/Vivado/%E5%85%B3%E4%BA%8Everilog%E5%AF%84%E5%AD%98%E5%99%A8%E5%AE%9A%E4%B9%89%E5%88%9D%E5%80%BC%E7%9A%84%E9%97%AE%E9%A2%98/td-p/1140068

问题

您好,我对于verilog下寄存器初值的问题(以下面代码为例),听到有两种说法:


// verilog
reg [7:0] test_reg = 8’b1111_0000 ;


1. 寄存器的初值与工艺和器件有关,因此无论我在定义寄存器时给的初值为何值,其都会在上电时根据不同器件,变为全’0’或全’1’。

2.寄存器定义时初值就是其上电初值。(并且新版fpga已经不再建议在always块中使用reset)。

我在搜索引擎中没能搜到这个问题官方的答案,请问这两种说法哪种更加正确?

回答

2.寄存器定义时初值就是其上电初值。(并且新版fpga已经不再建议在always块中使用reset)

这条正确, 尽量不用reset可以减少control set 的逻辑.

第一条有问题,相当于说初值的定义无法生效,这是不对的.

Altera器件是否也支持指定register初值

原文 https://community.intel.com/t5/Programmable-Devices/Register-initialization/m-p/141526#M42471


initial is for simulation only , it will get ignored during synthesis and will not initialize. quartus 2 has an option in the Assignment editor called Power Up Level. you set it’s value either 0 or 1. by default quartus initializes all registers to 0. link your register to that assignment, and set the value for it, to initialize a flip flop or a register to 1 when the system starts up.


This is untrue. Quartus now take initialisation values in code (aswell as async reset values) as the power up value. It has been doing this for several years!

结论: 也支持

what is control set

参考 ug949

Control Signals and Control Sets

A control set is the grouping of control signals (set/reset, clock enable and clock) that drives any given SRL, LUTRAM, or register. For any unique combination of control signals, a unique control set is formed. The reason this is an important concept is registers within a 7 series slice all share common control signals and thus only registers with a common control set may be packed into the same slice.

Designs with several unique control sets may have a lot of wasted resources, as well as fewer options for placement resulting in higher power and lower performance. Designs with fewer control sets have more options and flexibility in terms of placement, generally resulting in improved results. In UltraScale™ devices, there is more flexibility in control set mapping within a CLB. However, it remains a good practice to limit unique control sets to give maximum flexibility in placement of a group of logic.

结论:七系列器件少用reset的好处是简化control set。

When and Where to Use a Reset

FPGA devices have dedicated global set/reset signals (GSR). These signals initialize all registers to the initial value specified state in the HDL code at the end of device configuration.

If an initial state is not specified, it defaults to a logic zero. Accordingly, every register is at a known state at the end of configuration, regardless of the reset topology specified in the HDL code. It is not necessary to code a global reset for the sole purpose of initializing the device on power-up.

RobertLiang

A post-graduate in USTC.

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