[reprint]SignalTap – II question problem: Unable to view certain internal registers in SignalTap II

[reprint]SignalTap – II question problem: Unable to view certain internal registers in SignalTap II

For a register that doesn’t drive anything(so it may be something like a counter I add for debug and just want to SignalTap), I have used stuff like the following without problem. (* noprune *) reg [2:0] status_count; This just prevents it from being synthesized out, and the register should be available pre-synthesis and post-fit STP.  For a wire, I have used (* keep *). This ensures that it is the output of a LUT and can be tapped post-fit. Wires should not need this if you are doing pre-synthesis tapping. That being said, if a wire would get synthesized out for other reasons, e.g. let’s say it doesn’t go anywhere, then the keep won’t prevent that. You could have it drive a register with the noprune attribute.  That is what has worked for me, but I’m guessing something else is going wrong since your snippets of code seem to try most possibilities.

If grabbing a register that doesn’t get synthesized out, then there should be no need for these attributes. Most SignalTap users never apply these attributes. I recommend tapping registers with SignalTap, but if you want to grab a wire and do it post-fit, then the keep is often necessary. The only reason to do post-fit is that you don’t have to do a full compile again. If you don’t mind doing that, then pre-synthesis is much easier. (This is because synthesis can keep any wire you tap or anything like that. Post-fit is the design synthesized down to LUTs and regs, and if a name has been lost there is no way to get it back).  Pre-syntheis and post-fit are separate from modelsim. If you can find the issue in modelsim, that is by far the better way to go. SignalTap is for hunting down bugs that occur in hardware but not in your simulation. That may be because your hardware has cases/complications that are not in your testbench. It may be because you have invalid timing constraints that don’t show up in simulation(like a bus passing between two unrelated clock domains). There are all sorts of reasons hardware doesn’t work and the user can’t find it in their simulations. That is when to use SignalTap. The reason to choose post-fit is that: a) You don’t have to run a full compile, which can be a pain when it’s an 8 hour compile, or: b) It’s a problem that jumps around, e.g. on one place-and-route you see it, but then you add SignalTap and recompile from scratch(so everything gets a new fit) and the problem goes away. Post-fit allows you to lock down the locations of that previous fit.

noprune Verilog HDL Synthesis Attribute

A Verilog HDL synthesis attribute that prevents the Quartus® Prime software from removing a register that does not directly or indirectly feed a top-level output or bidir pin, such as a fan-out free register. This attribute differs from the preserve attribute, which prevents a register from being reduced to a constant or merged with a duplicate register. Standard synthesis optimizations remove nodes that do not directly or indirectly feed a top-level output pin or bidir pin.

You may wish to retain a fan-out free register in many cases, for example, if you are compiling a preliminary design that will eventually include fan-out logic for the register. You may also intend to use the register for debugging in the Signal Tap Logic Analyzer. Finally, you may want to route from the register to a Signal Probe Pin after compilation.

Internally, the Quartus® Prime software implements a noprune attribute using the Preserve Fan-out Free Register Node logic option. For information about device support for the noprune attribute, see the Preserve Fan-out Free Register Node logic option.Note: Analysis & Synthesis also recognizes the synonymous synthesis attribute syn_noprune. This synthesis attribute behaves identically to the noprune synthesis attribute.

You can use Verilog 2001 attribute syntax to preserve a fanout-free register, as shown in the following code:

(* noprune *) reg reg1;

You can also embed the attribute in a block comment that follows the register’s variable declaration.

For example, in the following code, the comment /* synthesis noprune */ directs Analysis & Synthesis to preserve the fanout-free register reg1:

reg reg1 /* synthesis noprune */;


A post-graduate in USTC.

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