In the project flow, Vivado keeps track of dependencies. As you invoke a particular step, the tool ensures that the previous step is complete.
For example, if you want to run implementation, Vivado will check that synthesis has been performed and completed.
Dependency management also checks that the previous step has completed with the current set of inputs. That way, the tool ensures that the previous stage’s output is not stale.
For example, say you had performed synthesis, and subsequently you modified one of the RTL files. Even though synthesis is complete, it is stale because an input was modified after synthesis.
In a Vivado context, this situation is called “Out of Date.”
Sometimes, you might see synthesis (or another step) go out of date even when you make changes that should not impact synthesis.
For example, after synthesis you add a “pblock” constraint, which does not impact synthesis. However, synthesis shows up as out of date.
This happens because of the level of granularity at which Vivado tracks dependency.
Synthesis depends on the input HDL, the XDC, and other factors. When the tool sees a change to the XDC (due to the addition of pblocks), it sees an input ingredient change. As a result, synthesis is declared to be out of date.
It does not track individual commands within the XDC, to check whether or not they impact synthesis.
The above has been designed with the philosophy of keeping the dependency tree relatively light-weight, and also to err on the side of being pessimistic.
If you encounter such a situation, go to the “Design Runs” window, right click on the synthesized view and select “Force Up to Date”. Now, you are ready to move to the next stage of the flow. Understand that you have now taken on the responsibility for ensuring that synthesis is actually valid and current.
So, when you force Synthesis to become Up-to-Date, you need to make sure that:
- You understand the exact change made that caused the synthesis to be Out-of-Date in the first place
- The specific change should not really impact synthesis
A great comment
I want to point out that you have some amount of control over this.
The specific example given (changing a pblock) can be done in a way such that it does not affect the “up to date” status of synthesis…
Each XDC file added to a project has a property which dictates during which processes it is required. In project mode this are the “USED_IN_SYNTHESIS” and “USED_IN_IMPLEMENTATION” properties.
If you want to isolate your synthesis from changes in constraints that only affect implementation, then set up your projects with different XDC files
– one file that contains all timing constraints and any other constraints that are required by synthesis and implementation
– leave the USED_IN… at the default value, which is both USED_IN_SYNTHESIS and USED_IN_IMPLEMENTATION
– on file that contains only physical constraints
– these include:
– I/O locatitions and attributes (I/O standards, drive strength, etc…)
– internal LOC constraints
– PBLOCK constraints
– set only the “USED_IN_IMPLEMENTATION” on this file (and don’t set “USED_IN_SYNTHESIS”)
With this setup, any change you make to the XDC file that is marked as only “USED_IN_IMPLEMENTATION” will not cause the synthesis to go out of date – the dependency management system in Vivado pays attention to these properies.