[reprint] operand(s) in condition matching error.

[reprint] operand(s) in condition matching error.

Verilog HDL Conditional Statement error at <location>: cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct(ID: 10200)

CAUSE:In a conditional statement at the specified location in a Verilog Design File (.v), you specified a condition that Quartus II Integrated Synthesis cannot use to classify the edges in the enclosing always construct’s event control. When an event control contains multiple edges, Quartus II Integrated Synthesis distinguishes the asynchronous control signals from the clock by analyzing the conditional statements in the always construct. For example, the following code fragment contains an always construct whose event control contains three edges—two asynchronous resets and a clock.always @ (posedge clk or posedge rst1 or posedge rst2) begin
if ( rst1 || rst2 )
q <= 1’b0;
else
q <= d;
end
Quartus II Integrated Synthesis uses the if condition to identify the two asynchronous resets and, by implication, the clock. For edge classification, Quartus II Integrated Synthesis requires that a condition fall into one of two categories. It can refer to a single edge identifier (to match posedge events) or its complement (to match negedge events), for example, rst1!rst1rst1 == 1'b1rst1 == 1'b0. It can also OR two or more expressions that each refer to a single edge identifier or its complement, for example, (rst1 || rst2)(!rst1 || !rst2).You can receive this error if your condition tests for the wrong polarity, or if it tests for the value of a variable that is not an edge in the event control. For example, to match a posedge rst event, the condition must be rst or rst = 1'b1.Finally, you can receive this error if you are attempting to use a single condition expression to test for both an asynchronous reset/set and a synchronous reset/set condition. The following code fragment contains an example of an illegal condition expression:always @ (posedge clk or posedge rst) begin
if ( rst || sync_rst )
q <= 1’b0;
else
q <= d;
end
Quartus II Integrated Synthesis generates this error message when compiling this design because it cannot match sync_rst to an edge on the sensitivity list.
ACTION:Modify the condition(s) or the conditional statement(s) so that Quartus II Integrated Synthesis can properly classify the edges in the event control of the always construct. For example, you could rewrite the previous example with the illegal synchronous reset test as follows:always @ (posedge clk or posedge rst) begin
if (rst1)
q <= 1’b0;
else if (sync_rst)
q <= 1’b0;
else
q <= d;
end

See also:

Section 9.4 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

总结:硬件实施的要求,不允许在 always 块中出现的边沿触发条件与其他信号同时构成 if 语句的条件。

我猜测这是因为,EDA工具需要根据 if 语句中对 边沿触发的敏感信号进行分类,而其他信号的存在会影响其分类。从硬件综合的角度来看,reset 信号显然是 D 触发器的异步复位端,这是 EDA 工具根据 if 语句判断的。而其他信号放入 if 中,并不允许被接到该 D 触发器的异步复位端。

RobertLiang

A post-graduate in USTC.

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